A critical analysis of the RISC-V instruction set architecture argues that its design flaws, excessive optionality, and fragmented ecosystem hinder its viability for high-performance computing and desktop applications.

Key Points

• The author contends that RISC-V’s "infinite optionality" creates incompatible hardware implementations, forcing developers to target the lowest common denominator.
• Interrupt handling in RISC-V is criticized as significantly slower and more complex than the industry-standard ARM Cortex-M0.
• The architecture lacks essential features like register-plus-register addressing modes, which the author claims were ignored for years before being added as optional extensions.
• Compressed instruction encodings are described as poorly designed, with inconsistent immediate values and overlapping bit patterns that can cause semantic errors.
• The author predicts RISC-V will succeed primarily in low-cost, single-use microcontroller markets where price is the deciding factor rather than architectural quality.

Why it Matters

The critique highlights a growing tension between the open-source nature of the RISC-V specification and the practical requirements of software compatibility and performance. As major distributions like Android and Linux move toward mandatory profiles like RVA23, the industry faces a potential divide between "standard-compliant" hardware and the vast array of existing, fragmented RISC-V implementations.