TSMC is accelerating the development of CoPoS panel-level packaging and glass core substrate technology to replace CoWoS, aiming to increase AI chip production efficiency and reduce manufacturing costs.

Key Points

• TSMC plans to transition from circular wafers to rectangular panels, increasing material utilization from under 70% to over 90%.
• CoPoS technology utilizes larger panel sizes, such as 750x620mm, to accommodate more compute dies and memory modules per unit.
• The company targets trial production for CoPoS by 2027, with full-scale mass production expected to begin in 2028.
• TSMC is collaborating with partners including Ibiden and Innolux to develop a three-layer glass core substrate design.
• The Arizona facility is slated to play a significant role in CoPoS production between 2029 and 2030.

Why it Matters

This shift toward panel-level packaging and glass substrates addresses the physical limitations and rising costs associated with manufacturing increasingly large AI chips. By improving yield and scalability, these technologies are essential for meeting the surging global demand for high-performance computing hardware.